1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the invention relates to technology that can be effectively utilized for a semiconductor integrated circuit device having a clock-generating circuit for generating clock signals corresponding to clock signals supplied through an external terminals, and that can be effectively utilized chiefly for a synchronous dynamic RAM (random access memory).
2. Prior Art
As a semiconductor integrated circuit device having a digital circuit that operates on clock signals supplied through an external terminal, there has been known a DLL (delay locked loop) which is a circuit for bringing the clock signals supplied through the external terminal into synchronism with the internal clock signals to increase the frequency of the clock signals while preventing reduction in the timing margin caused by a delay relative to the clock signals supplied to the internal circuit. The DLL is constituted by a variable delay circuit for varying the amount of delay and a control circuit for controlling the amount of delay. The phase-synchronizing circuits have been disclosed in Japanese Patent Laid-Open Nos. 90666/1990, 55145/1999 and 171774/1998.